Semiconductor Engineering

Power-Aware Test: Addressing Power Challenges In DFT And Test

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design ...
Semiconductor Engineering

Packetized Scan Test

Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping ...
Electronic Design

What’s Next for Physically Aware DFT?

Why isolated flows negatively impact design schedule and PPA. Benefits of unified DFT, synthesis, and physical design flows. Physical implementation optimization methods for test compression and scan ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
EDN

ITC tutorials span DFT basics to RF test

The 2006 International Test Conference is scheduled for the week of October 22 in Santa Clara, CA. For more on this year’s ITC, read our interview with program chair Anne Gattiker. Semiconductor test ...